Cadence and TSMC have expanded certified AI and HPC design flows across advanced nodes, chiplets and 3D-ICs.

SAN JOSE, Calif. & HSINCHU, Taiwan--(BUSINESS WIRE)--United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) (UMC), a leading global semiconductor foundry, and Cadence Design Systems, Inc. (Nasdaq ...

Expanded partnership spans TSMC A14 certification, silicon-proven IP on TSMC N3P/N2P, wafer-scale 3D-IC for hundreds of chiplets, and agentic AI flows. SAN JOSE, Calif.-- Cadence ...

Cadence and TSMC are expanding their collaboration by achieving tool certification for the next-gen A14 process technology.

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its ...

Proven interface IP architectures realized significant gains in performance and power efficiency on the TSMC N3E process 224G-LR SerDes PHY IP on the TSMC N3E process has achieved first-pass silicon ...

Cadence Design Systems and Synopsys have achieved certification for key design flows on TSMC's A14 process, expanding the design ecosystem for the foundry's next full node ahead of risk production in ...

Semiconductors are becoming even more complicated as their makers use chiplets, die stacking and new architectures to adapt to the needs of the AI-powered world. In this context, chip equipment and ...

Expanded cooperation spans DTCO, IP readiness and design enablement to advance next-generation customer innovation SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence (Nasdaq: CDNS) today announced an ...

Physical AI is a systems challenge, requiring a complete foundation that connects AI models to trusted silicon and ultimately ...

Cadence (Nasdaq: CDNS) today announced an expanded collaboration with Intel Foundry to advance Design Technology Co-Optimization (DTCO) targeting Intel’s next-generation process technologies, ...