EDN

Taking power analysis to the transistor level for a full chip

Almost every chip being taped out today is mixed-signal in nature. In addition to increased integration of analog and RF blocks, designers are using complex power-management techniques to minimize ...
동아사이언스

KAIST predicts sub-4 nm transistor scaling with atomic-level design platform

A Korean research team has developed a computational design platform that uses atomic-level simulations to predict how much smaller semiconductor transistors can become. Their calculations show that, ...
Semiconductor Engineering

Setting Vmin With Transistor-Level PDN Telemetry

Curious about how to precisely determine the optimal voltage-regulator setpoints for your System-on-Chip (SoC)? In this video, we dive into how transistor-level Power Delivery Network (PDN) telemetry ...
EDN

Synopsys Rolls Out Transistor-Level Static Timing Analysis

To address emerging custom circuit design challenges, Mountain View, Calif.-based EDA giant Synopsys Inc. today unveiled its anticipated next-generation transistor-level static timing analysis tool, ...
Electronic Design

GaN Transistors – Drive Control, Thermal Management, and Isolation

This year, several companies are expected to bring 600/650 V Gallium Nitride (GaN) power transistors to market. Almost all will be normally-on (depletion mode) transistors connected in a cascode ...
Nanowerk

Single-Electron Transistors: The Ultimate in Miniaturization and Precision

What is a Single-Electron Transistor? A single-electron transistor (SET) is a nanoscale electronic device that allows the precise control of individual electrons. Unlike conventional transistors that ...
Phys.org

Scientists discover way to 'grow' sub-nanometer sized transistors

A research team led by Director Jo Moon-Ho of the Center for Van der Waals Quantum Solids within the Institute for Basic Science (IBS) has implemented a novel method to achieve epitaxial growth of 1D ...