IEEE

Power efficient scan testing by exploiting existing error tolerance circuitry in a design

Abstract: Timing errors are a major threat in modern integrated circuits. Suitable error tolerance design techniques exist, like Razor, aiming to confront with this ...
IEEE

On the reuse of existing error tolerance circuitry for low power scan testing

Abstract: Timing errors are a major threat in nanometer technology integrated circuits. Razor is a well known timing error tolerance design technique. However, its ...