ST. LOUIS (SC25) — Nov 17, 2025 – Generative AI inference compute company d-Matrix and Andes Technology , a supplier of RISC-V processor cores, announced that d-Matrix has selected the AndesCore ...

The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...

RISC (reduced instruction set computer), and CISC (complex instruction set computer). These two principles govern fundamental choices of CPU design and implementation. RISC architectures, such as ARM, ...

SANTA CLARA, Calif.--(BUSINESS WIRE)--Further expanding SiFive’s lead in RISC-V AI IP, the company today launched its 2nd Generation Intelligence™ family, featuring five new RISC-V-based products ...

China is ramping up its RISC-V ambitions with the launch of the Shanghai Open Source Computing Research Institute, unveiled at the 5th RISC-V Summit China on July 17, 2025. As the country's second key ...

Boundless, the decentralized zero-knowledge (ZK) compute marketplace powered by RISC Zero, has launched its incentivized testnet (which it is calling “Mainnet Beta”) on Base, Coinbase’s Ethereum layer ...

HiSilicon (Shanghai) Technologies — Huawei's application-specific chip design arm known as "Little HiSilicon" — has launched a broad lineup of self-developed chips spanning IoT, industrial automation, ...

The industry is increasingly talking about benefits brought by the RISC-V architecture, but is it even the right starting point? While it may not be perfect, it may provide the flexibility necessary ...

ECARX launched its RISC-V-based EXP01 processor and outlined its automotive-grade MCU roadmap at the RISC-V Summit Europe 2025. ECARX Holdings Inc., a global mobility tech provider, introduced its ...

A lab develops brain wave decoder that may help in spinal cord injury rehabilitation. When a person sustains an injury to the spinal cord, the normal communication between the brain and the spinal ...